On the Mathematical Models Characterizing Faulty Four-Phase MOS Logic Arrays

In earlier papers no analysis characterizing faulty four-phase MOS logic arrays due to single load and sampling transistor faults has been given. In this note the models due to faulty load and sampling transistors are analyzed and discussed. Some useful results leading to faster simulation of four-phase MOS logic arrays with single faulty load and sampling transistors are presented. The computer simulation run time is reduced by one half for single-load transistor faults. At the end of each bit a shorted sampling transistor does not introduce any error for gate types 2 and 3 when initialization is with phase-4 time and for gate types 1 and 4 when initialization is with phase-2 time.