DocumentCode :
959247
Title :
Minimal Input-Memory and Output-Memory Finite-State Machines
Author :
Vairavan, K.
Author_Institution :
Department of Electrical Engineering, University of Wisconsin-Milwaukee, Milwaukee, Wis. 53201.
Issue :
6
fYear :
1972
fDate :
6/1/1972 12:00:00 AM
Firstpage :
598
Lastpage :
602
Abstract :
A finite-state machine (FSM) is said to have finite input-memory, ¿i (finite output-memory ¿o) if ¿i(¿o) is the least integer such that yk = f(Xk, Xk-1,..., Xk-¿i), (yk = f(Xk, yk-1,..., yk-¿o)). If no such integer ¿i(¿o) exists then by convention ¿i = ¿ (¿ = ¿). It is well known that for a nondegenerate binary-input binary-output FSM M, ¿i ¿ [log2 n] (¿o ¿ [log2 n]), where n is the number of non-equivalent states in M. In this note we show that the above bound cannot be improved upon by giving a procedure to construct, for any n ≫ 0, a binary-input binary-output FSM with n nonequivalent states and minimal input-memory ¿i = [log2 n] (minimal output-memory ¿o = [ log2 n]). In the process of proving the tightness of the lower bound on ¿i(¿o), we enumerate the number of distinct minimal binary r-stage feed-forward (output feedback) shift registers.
Keywords :
Feedforward systems; Logic; Output feedback; Shift registers; State feedback; Finite input memory; finite; minimal shift register realizations; output memory; sequential machines;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1972.5009017
Filename :
5009017
Link To Document :
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