DocumentCode :
959378
Title :
Scan-based transition test
Author :
Savir, Jacob ; Patil, Srinivas
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
Volume :
12
Issue :
8
fYear :
1993
fDate :
8/1/1993 12:00:00 AM
Firstpage :
1232
Lastpage :
1241
Abstract :
Skewed-load transition test is a form of scan-based transition test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. In the skewed-load test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector of the pair (the one that launches the transition) is required to be the next (i.e., one-bit-shift) pattern in the scan chain. Although a skewed-load transition test is attractive from a timing point of view, there are various problems that may arise if this strategy is used. Here, several issues of skewed-load transition test are investigated. Issues such as transition test calculus, detection probability of transition faults, transition fault coverage, and enhancement of transition test quality are thoroughly studied
Keywords :
boundary scan testing; delays; fault location; logic testing; probability; AC test; clock speed; combinational logic; delay fault models; delay test; detection probability; scan-based transition test; skewed-load test protocol; transition fault coverage; transition test calculus; Circuit faults; Circuit testing; Clocks; Combinational circuits; Jacobian matrices; Latches; Logic circuits; Logic testing; Propagation delay; Protocols;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.238615
Filename :
238615
Link To Document :
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