Title :
Reconfiguration and analysis of a fault-tolerant circular butterfly parallel system
Author :
Tzeng, Nian-Feng
Author_Institution :
Center for Advanced Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
fDate :
8/1/1993 12:00:00 AM
Abstract :
The butterfly parallel system has a regular and simple interconnection pattern, making it suitable for VLSI or WSI implementation. The authors propose an effective fault-tolerant technique for the circular butterfly parallel system to ensure its rigid full butterfly structure even in the presence of failures, addressing reconfiguration in detail. The resulting butterfly system has L levels, involves (1/log2 L)% spare processing elements (PEs), and approximately 50% additional links. The reconfiguration process of the design in response to any operational fault is easy and can be performed in a distributed manner. The reliability and layout of this proposed design are evaluated analytically. This design, due to its specific configuration, exhibits significant improvement in reliability while taking only moderately more layout area
Keywords :
fault tolerant computing; multiprocessor interconnection networks; reconfigurable architectures; VLSI; WSI; fault-tolerant circular butterfly parallel system; interconnection pattern; reconfiguration; spare processing elements; Degradation; Environmental economics; Fault tolerant systems; Hardware; Parallel architectures; Process design; Reliability; Topology; Very large scale integration; Wafer scale integration;
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
