Title :
On the Bandwidth and Interference in Interleaved Memory Systems
Author_Institution :
Department of Electrical Engineering and Computer Science, University of California, Berkeley, Calif. 94720.
Abstract :
A model to estimate the bandwidth and interference in an interleaved memory system in a multiprocessor system is described. The model allows queuing on busy modules, and the results obtained show that previous results are rather pessimistic.
Keywords :
Adders; Bandwidth; Control system synthesis; Feeds; Flexible printed circuits; Instruments; Integrated circuit synthesis; Interference; Logic design; Pulse circuits; Interference; interleaved memory; memory bandwidth;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1972.5009049
