A discussion on the temperature dependence of latch-up trigger current in CMOS/BiCMOS structures

The measured temperature dependence of latch-up trigger currents in CMOS/BiCMOS structures from 10 to 125 °C is quantitatively discussed based on a simple lumped element equivalent model. Temperature coefficients of the p-well and n-well trigger currents for three different well structures are around -1.0%/°C and -0.6%/°C, respectively. The latch-up trigger currents calculated using temperature dependent parasitic parameter values such as the current gains of parasitic bipolar transistors, the forward emitter-base voltage, and parasitic well shunting resistances are in good agreement with the measured ones. In addition, the role each parameter plays in reducing latch-up trigger currents at higher temperature is clarified