DocumentCode :
960531
Title :
Characterization and high-speed digital application of GaAs MESFETs on substrates
Author :
Onozawa, S. ; Yamamoto, Naoji ; Kimura, Tomohiro ; Sano, Yousuke ; Akiyama, Masanori
Author_Institution :
Oki ELectr. Ind. Co. Ltd., Tokyo
Volume :
40
Issue :
11
fYear :
1993
fDate :
11/1/1993 12:00:00 AM
Firstpage :
2139
Abstract :
Summary form only given. The authors optimized the device structure to suppress the short channel effect due to the residual stress in GaAs/Si substrates and improved the microscopic uniformity. The residual-stress problem was solved by introducing a p-layer (C+ : 140 keV) buried under the n-type channel (Si+: 20 keV) in the n+ self-alignment technique with refractory W-Al gate. The authors then evaluated the microscopic uniformity of the device on GaAs/Si using 60-μm×60-μm-pitch FET arrays, and found that it is improved by introducing the p-layer. To evaluate the dynamic characteristics, a direct-coupled FET logic (DCFL) ring oscillator was fabricated using a 0.3-μm-gate MESFET on the GaAs/Si substrate. The propagation delay was as small as 19.9 ps/gate at a supply voltage of 2 V
Keywords :
III-V semiconductors; Schottky gate field effect transistors; direct coupled FET logic; field effect integrated circuits; gallium arsenide; integrated logic circuits; 0.3 micron; 2 V; FET arrays; GaAs-Si; Si; device structure; direct-coupled FET logic; dynamic characteristics; microscopic uniformity; n+ self-alignment technique; propagation delay; residual stress; ring oscillator; short channel effect; Fabrication; Gallium arsenide; High temperature superconductors; MESFETs; SQUIDs; Silicon; Substrates; Superconducting devices; Superconducting films; Yttrium barium copper oxide;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.239825
Filename :
239825
Link To Document :
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