Title :
On Possible Thermal Degradation in Spirally Programmed Interconnection Wafer Technology
Author_Institution :
University of St.Andrews,Scotland, U.K
fDate :
3/1/1981 12:00:00 AM
Abstract :
A possible cause of difficulty in utilizing spiral programmed interconnection in full wafer technology is examined. This is the existence of hot spots. It is shown that hot spots are likely to occur and, in which case, to impair seriously the wafer performance. Means of avoiding such degradation are indicated.
Keywords :
Integrated circuit metallization; Integrated circuit thermal factors; Costs; Integrated circuit interconnections; Manufacturing; Packaging; Spirals; Temperature; Thermal degradation; Thermal resistance; Very large scale integration; Wafer scale integration;
Journal_Title :
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
DOI :
10.1109/TCHMT.1981.1135775
