DocumentCode
960836
Title
Identification of Multiple Stuck-Type Faults in Combinational Networks
Author
Breuer, Melvin A. ; Chang, Shih-Jeh ; Su, Stephen Y H
Author_Institution
Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90007.
Issue
1
fYear
1976
Firstpage
44
Lastpage
54
Abstract
This paper deals with the problem of identifying multiple stuck-type hardware failures in combinational switching networks. Our work is an extension of that of Poage, and Bossen and Hong, and we employ the cause-effect equation for representing faulty circuit behavior. We introduce the concept of solving simultaneous equations over check point variables. These check point solutions are studied in detail. From the solutions one can calculate the function realized by a faulty circuit. We outline an on-line testing procedure for constructing a test set for identifying a specific fault in a circuit to within an equivalence class. This procedure eliminates the need for precalculating a fault dictionary, which, in many instances, can be quite advantageous. We also outline how to apply these techniques to the following problems: 1) identifying redundancy; 2) determining the set of faults not detected by an arbitrary test set; and 3) constructing a complete fault dictionary.
Keywords
Circuit faults; Circuit testing; Combinational circuits; Dictionaries; Equations; Fault detection; Fault diagnosis; Fault location; Large scale integration; Logic arrays; Combinational networks; diagnosis; fault location; multiple faults; on-line testing; stuck-at-faults;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1976.5009204
Filename
5009204
Link To Document