High-speed VLSI interconnect modeling based on S-parameter measurements

Author

Eo, Yungseon ; Eisenstadt, William R.

Author_Institution

Dept. of Electr. Eng., Florida Univ., Gainseville, FL, USA

Volume

16

Issue

5

fYear

1993

fDate

8/1/1993 12:00:00 AM

Firstpage

555

Lastpage

562

Abstract

A first-level-metal single-conductor IC interconnect model is developed for high-speed and high-density VLSI circuit design. The model shows interconnect circuit parameters that vary with frequency. Existing interconnect models exclude effects such as capacitive fringing and the influence of substrate conductance. The new model represents fine-line as well as wide-line interconnect behavior over a 20-GHz frequency range and includes these effects. The model parameters are compared to scattering parameter measurements as well as numerical simulations based on PISCES-II. Excellent agreement is shown with S-parameter measurements

Keywords

S-parameters; VLSI; capacitance; dielectric losses; equivalent circuits; inductance; integrated circuit technology; metallisation; permittivity; semiconductor device models; 0 to 20 GHz; PISCES-II; S-parameter measurements; VLSI interconnect modeling; capacitive fringing; circuit parameters; fine-line; first-level-metal; high-density; high-speed; numerical simulations; scattering parameter measurements; single-conductor IC interconnect; substrate conductance; wide-line interconnect behavior; Circuit synthesis; Conductors; Frequency measurement; Integrated circuit interconnections; Integrated circuit measurements; Integrated circuit modeling; Integrated circuit testing; Scattering parameters; Substrates; Very large scale integration;

fLanguage

English

Journal_Title

Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Publisher

ieee

ISSN

0148-6411

Type

jour

DOI

10.1109/33.239889

Filename

239889