• DocumentCode
    962132
  • Title

    Cascading Transmission Gates to Enhance Multiplier Performance

  • Author

    Shively, R.R. ; Robinson, W.V., Jr. ; Orton, D.E.

  • Author_Institution
    AT&T Bell Laboratories, Whippany, NJ 07981.
  • Issue
    7
  • fYear
    1984
  • fDate
    7/1/1984 12:00:00 AM
  • Firstpage
    677
  • Lastpage
    679
  • Abstract
    A high-speed Wallace-tree type combinational multiplier chip has been fabricated as a technology demonstration device using 1.5 ¿m NMOS processing. Multiply rates well in excess of 40 mHz have been obtained from laboratory devices. Extensive use of cascaded MOS transmission-gate (or steering) logic resulted in worthwhile improvements in power, average gate delay, and device topology.
  • Keywords
    Circuit theory; Electrons; Feedback; Polynomials; Sequential circuits; Shift registers; Booth´s algorithm; VLSI; Wallace multiplier; fineline NMOS; logic design; multiplier chip; transmission gate;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1984.5009343
  • Filename
    5009343
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=962132