Title :
Cascading Transmission Gates to Enhance Multiplier Performance
Author :
Shively, R.R. ; Robinson, W.V., Jr. ; Orton, D.E.
Author_Institution :
AT&T Bell Laboratories, Whippany, NJ 07981.
fDate :
7/1/1984 12:00:00 AM
Abstract :
A high-speed Wallace-tree type combinational multiplier chip has been fabricated as a technology demonstration device using 1.5 ¿m NMOS processing. Multiply rates well in excess of 40 mHz have been obtained from laboratory devices. Extensive use of cascaded MOS transmission-gate (or steering) logic resulted in worthwhile improvements in power, average gate delay, and device topology.
Keywords :
Circuit theory; Electrons; Feedback; Polynomials; Sequential circuits; Shift registers; Booth´s algorithm; VLSI; Wallace multiplier; fineline NMOS; logic design; multiplier chip; transmission gate;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1984.5009343
