Title :
A Novel Wafer-Yield PDF Model and Verification With 90–180-nm SOC Chips
Author :
Masuda, Hiroo ; Tsunozaki, Manabu ; Tsutsui, Toshikazu ; Nunogami, Hiroyuki ; Uchida, Akihisa ; Tsunokuni, Kazuyuki
Author_Institution :
SOC Device Design Dept., Renesas Technol. Corp., Tokyo
Abstract :
In this paper, we describe a new wafer-yield distribution model, which agrees well with experiment using fabricated products with various process technologies. To investigate physical reasoning of the proposed model, we firstly measure effective defect density of chips regarding to spatial dependency in a wafer. It is clarified that the defect density near wafer edge is a couple of times larger than that at the rest of wafer area. Note that the increase of defect at wafer edge causes a significant yield loss in production process lines.
Keywords :
defect states; integrated circuit yield; mass production; nanoelectronics; probability; semiconductor process modelling; system-on-chip; wafer-scale integration; SOC chips; effective defect density; mass production process; mass production process lines; probability density function; size 90 nm to 180 nm; wafer-yield distribution model; yield loss; Density measurement; Helium; Lithography; Logic; Mass production; Predictive models; Semiconductor device measurement; Semiconductor device modeling; Statistical distributions; Technology management; Defect density; PDF; distribution model; spatial statistics; wafer-yield;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
DOI :
10.1109/TSM.2008.2005317
