Title :
Memory cell and technology issues for 64- and 256-Mbit one-transistor cell MOSD DRAMs
Author :
Tasch, Al F., Jr. ; Parker, Laureen H.
Author_Institution :
Microelectron. Res. Center, Texas Univ., Austin, TX, USA
fDate :
3/1/1989 12:00:00 AM
Abstract :
The memory cell and technology requirements and issues for 64- and 256-Mb MOS DRAMs (dynamic random-access memories) based on the charge storage concept (one-transistor cell) are analyzed. Projected requirements have been developed for key parameters such as die size, cell area, charge capacity, storage capacitance and area, leakage current, and on-current. These requirements are based on an analysis and assessment of expected improvements in soft error rate, sense amplifier sensitivity, 0-1 storage voltage difference, and bit line capacitance. Pivotal issues specific to the DRAM are identified. It is concluded that sufficient progress will be made so that 64-Mb DRAMs will be successfully produced in the early to mid-1990s.
Keywords :
MOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 256 Mbit; 64 Mbit; MOSD DRAMs; ULSI; bit line capacitance; cell area; charge capacity; charge storage concept; die size; dynamic random-access memories; key parameters; leakage current; memory cell; on-current; one-transistor cell; sense amplifier sensitivity; soft error rate; storage capacitance; storage voltage difference; technology issues; technology requirements; Capacitance; Costs; Error analysis; Integrated circuit technology; Leakage current; MOS capacitors; Magnetic cores; Performance analysis; Random access memory; Switches; Voltage;
Journal_Title :
Proceedings of the IEEE
