Title :
Novel PLL-based clock distribution scheme
Author :
Embabi, S.H.K. ; Islam, K.I.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
A technique for minimising clock skew in VLSI chips and multichip modules is proposed. A phase-locked loop is used to tune the delay of the clock interconnects. Negative, zero and positive delays can be achieved. This allows for clock synchronisation between individual modules with locally optimised clock distribution to minimise global clock-skew.
Keywords :
VLSI; clocks; delays; digital circuits; digital integrated circuits; error compensation; multichip modules; phase-locked loops; synchronisation; PLL-based clock distribution scheme; VLSI chips; clock interconnects; clock skew minimisation; clock synchronisation; delays; multichip modules; remote VCO;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19931206
