DocumentCode
963377
Title
The Arithmetic Cube
Author
Owens, Robert Michael ; Irwin, Mary Jane
Author_Institution
Department of Computer Science, The Pennsylvania State University, University Park, PA 16802.
Issue
11
fYear
1987
Firstpage
1342
Lastpage
1348
Abstract
We present the design of a VLSI processor which can be programmed to compute the discrete Fourier transform of a sequence of n points and which achieves the theoretical AT2 lower bound of ¿(n2) for n ¿ n where n is an infinite set. Furthermore, since the set n is also sufficiently dense, the processor achieves for any n the theoretical AT2 lower bound of ¿(n2) for computing the cyclic convolution of two sequences of n points. Uniquely, our design achieves this bound without the use of data shuffling or long wires. Also, the processor uses only approximately ¿n multipliers, while many other designs need ¿(n) multipliers to achieve the same time bounds. Since multipliers are usually much larger than adders, the processor presented in this paper should be smaller. The design also features layout regularity, minimal control, and nearest neighbor interconnect of arithmetic cells of a few different types. These characteristics make it an ideal candidate for VLSI implementation.
Keywords
Arithmetic; Computer architecture; Convolution; Data flow computing; Discrete Fourier transforms; Fourier transforms; Nearest neighbor searches; Signal processing algorithms; Very large scale integration; Wires; Cyclic convolution; VLSI architecture; digital signal processing; discrete Fourier transform; mixed radix; prime factor; systolic architecture;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1987.5009473
Filename
5009473
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