• DocumentCode
    964101
  • Title

    Testing layered interconnection networks

  • Author

    Liu, Bin ; Lombardi, Fabrizio ; Park, Nohpill ; Choi, Minsu

  • Author_Institution
    Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
  • Volume
    53
  • Issue
    6
  • fYear
    2004
  • fDate
    6/1/2004 12:00:00 AM
  • Firstpage
    710
  • Lastpage
    722
  • Abstract
    We present an approach for fault detection in layered interconnection networks (LINs). An LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. Switching elements (made of simple switches such as transmission-gate-like devices) are arranged in a cascade to connect pairs of layers. The switching elements of an LIN have the same number of switches, but the switching patterns may not be uniform. A comprehensive fault model for the nets and switches is assumed at physical and behavioral levels. Testing requires configuring the LIN multiple times. Using a graph approach, it is proven that the minimal set of configurations corresponds to the node disjoint path sets. The proposed approach is based on two novel results in the execution of the network flow algorithm to find node disjoint path sets, while retaining optimality in the number of configurations. These objectives are accomplished by finding a feasible flow such that the maximal degree can be iteratively decreased, while guaranteeing the existence of an appropriate circulation. Net adjacencies are also tested for possible bridge faults (shorts). To account for 100 percent fault coverage of bridge faults a postprocessing algorithm may be required; bounds on its complexity are provided. The execution complexity of the proposed approach (inclusive of test vector generation and post-processing) is O(N4WL), where N is the total number of nets, W is the number of switches per switching element, and L is the number of layers. Extensive simulation results are provided.
  • Keywords
    circuit testing; computational complexity; fault diagnosis; fault tolerance; graph theory; multistage interconnection networks; reconfigurable architectures; fault detection; fault tolerance; graph approach; layered interconnection network; multistage interconnection network; network flow algorithm; reconfigurable system; switching element; Bridges; Communication switching; Fault detection; Fault tolerance; Field programmable gate arrays; Iterative algorithms; Multiprocessor interconnection networks; Routing; Switches; System testing; 65; Fault detection; fault tolerance; layered interconnection networks; network flow.; switch;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2004.17
  • Filename
    1288546