DocumentCode :
964347
Title :
Optimal configuring of multiple scan chains
Author :
Narayanan, Sridhar ; Gupta, Rajesh ; Breuer, Melvin A.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Volume :
42
Issue :
9
fYear :
1993
fDate :
9/1/1993 12:00:00 AM
Firstpage :
1121
Lastpage :
1131
Abstract :
To reduce the high test time for serial scan designs, the use of multiple scan chains has been proposed. In this paper, the authors consider the problem of optimally constructing the multiple scan chains to minimize the overall test time. Rather than follow the traditional practice of using equal length chains, the authors allow the chains to be of different lengths and show that this cap lead to lower test times. The main idea in this approach is to place those scan elements that are more frequently accessed in shorter scan chains as this tends to reduce the overall test time. Given a design with N scan elements and given that if scan chains need to be used for applying tests, the authors present an algorithm of complexity O(kN2) for constructing the specified number of chains such that the overall test application time is minimized. By analyzing a range of different circuit topologies, the authors demonstrate test time reductions as large as 40% over equal length chains
Keywords :
computational complexity; design for testability; logic testing; complexity; dynamic programming; equal length chains; full scan; multiple scan chains; optimal chain configurations; partial scan; polynomial time complexity; serial scan designs; test time; test time reductions; Algorithm design and analysis; Circuit testing; Circuit topology; Costs; Degradation; Flip-flops; Pins; Polynomials; System testing; Test equipment;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.241600
Filename :
241600
Link To Document :
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