Design of a High Performance DIP-Like Pin Array Package for Logic Devices

Pin array packages offer package sizes which are much smaller than their dual in-line package (DIP) equivalent. Pin array packages are also through hole mountable. A pin array package is described which is DIP-like in that it is rectangular but the input/ output (I/O) pins do not fully populate its base. The package is a co-fired tungsten metallized multilayer ceramic package with 104 I/O´s yet is only 1.16 in wide by 1.88 in long. Dual tier wire bond ledges are used to minimize wire bond lengths which also enhances electrical performance. This package is used in systems where many leads must switch simultaneously onto a heavily loaded bus. Such switching may result in considerable electrical noise. To meet noise requirements the package had to have the lowest possible ground impedance. This was accomplished by dedicating 20 percent of all pins to power and ground and by strategically positioning them on the package. Power and ground planes were also placed within the layered ceramic package to further lower the ac ground impedance. Finally, these planes were arranged to provide nearly 1000 pF highquality built-in filter capacitance. Noise is further reduced by minimizing crosstalk within the package. The presence of ground planes helps lower interlead crosstalk by factors of three to ten. Resistance and capacitance loading of the signal paths are designed to be acceptably low. A simple packaging change allows all the signal nets to be electrically probed from the top of the package. The package, depending upon its configuration and use of heat sinks, also has the capability of handling high power integrated circuits (IC´s).