DocumentCode
964735
Title
Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling
Author
Engelmaier, Werner
Author_Institution
Bell Laboratories, Whippany, NJ, USA
Volume
6
Issue
3
fYear
1983
fDate
9/1/1983 12:00:00 AM
Firstpage
232
Lastpage
237
Abstract
An ana1ytica1 method is described which provides estimates to first order of the number of either power or envirnnmenta1 cyc1es 1eading to so1der joint fai1ure. Vari0us parameter variations such as so1der joint height, ceramic chip carrier (CCC) size, printed c1rcuit substrate (PCS) materia1, etc. are investigated and discussed and samp1e estimates for a 0.65 x 0.65-in CCC are given.
Keywords
Integrated circuit thermal factors; Integrated-circuit reliability testing; Printed circuits; Soldering; Capacitive sensors; Ceramics; Fatigue; Lead; Personal communication networks; Printed circuits; Soldering; Steady-state; Temperature; Thermal expansion;
fLanguage
English
Journal_Title
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher
ieee
ISSN
0148-6411
Type
jour
DOI
10.1109/TCHMT.1983.1136183
Filename
1136183
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