Task-flow architecture for WSI parallel processing

Author

Horst, Robert W.

Author_Institution

Tandem Comput. Inc., Cupertino, CA, USA

Volume

25

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

10

Lastpage

18

Abstract

The basics of task-flow architecture and the simulated wafer-scale implementation of flowing tasks (SWIFT), a register-transfer simulator that investigates the behavior of task-flow programs, are discussed. SWIFT simulates a ring of cells with two pipeline stages between successive cells. Each cell contains an arithmetic logic unit (ALU), a receive queue for holding incoming transmission packets, and a memory for storing memory packets (MPs). The chain wafer-scale integration (WSI) architecture that allows linear arrays to be configured from the working cells on a partially good wafer is applied to task-flow-machine implementations. Results from a limited Monte Carlo simulation run to predict yields for a 164-cell wafer configured using the chain WSI technique are presented. Results of a simulated sparse matrix-vector multiplication application of the task-flow architecture are also presented.<>

Keywords

digital simulation; parallel architectures; virtual machines; Monte Carlo simulation; SWIFT; receive queue; register-transfer simulator; ring of cells; simulated wafer-scale implementation of flowing tasks; task-flow architecture; wafer-scale integration; Computer aided instruction; Computer architecture; Concurrent computing; Costs; Delay; Integrated circuit technology; Parallel processing; Silicon devices; System performance; Very large scale integration;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.129041

Filename

129041