A high-density, self-aligned power MOSFET structure fabricated using sacrificial spacer technology

Author

Shenai, Krishna

Author_Institution

General Electric Corp. Res. & Dev. Center, Schenectady, NY, USA

Volume

39

Issue

5

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

1252

Lastpage

1255

Abstract

A novel power MOSFET structure fabricated using sacrificial spacer technology is described. Anisotropically etched sidewall oxide spacers were used to implement self-aligned shallow p⁺ surface diffused regions to reduce the p-base sheet resistance and its contact resistance. Vertical power DMOSFETs with V_DB=150 V and R_sp=9.7 mΩ-cm² were fabricated using this technology, where V_DB is the drain-source avalanche breakdown voltage and R_sp is the specific on-state resistance. The measured on-state resistance performance is a factor of 4 times smaller compared to commercially available power MOSFETs in the 150-V reverse blocking range

Keywords

insulated gate field effect transistors; power transistors; semiconductor technology; 150 V; DMOSFETs; anisotropic etch; blocking voltage; contact resistance; drain-source avalanche breakdown voltage; on-state resistance; p-base sheet resistance; power MOSFET structure; sacrificial spacer technology; self aligned structure; shallow p⁺ surface diffused regions; sidewall oxide spacers; specific on-state resistance; vertical MOSFETs; Anisotropic magnetoresistance; Avalanche breakdown; Breakdown voltage; Contact resistance; Electrical resistance measurement; Etching; MOSFET circuits; Power MOSFET; Space technology; Surface resistance;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.129119

Filename

129119