Low-K Dielectric Compatible Wafer-Level Compliant Chip-to-Substrate Interconnects

Performance, power, size, and cost requirements in the microelectronics industry are pushing for smaller feature size, innovative on-chip dielectric materials, higher number of interconnects at a reduced pitch, etc., without compromising the microelectronics reliability. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill material. These compliant interconnects are beneficial for integrated circuits (ICs) with low-K dielectric material. They are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we discuss the assembly and experimental reliability assessment, through thermal cycling, of G-Helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented. It is shown that the proposed interconnects are not likely to delaminate or crack the low-K dielectric material. Also, a unique integrative approach is discussed, with interconnects having varying compliance for optimum electrical and mechanical performance.