DocumentCode :
967096
Title :
1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18- 
CMOS Technology
Author :
Han, Pyung-Su ; Choi, Woo-Young
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul
Volume :
54
Issue :
1
fYear :
2007
Firstpage :
38
Lastpage :
42
Abstract :
A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0deg and 180deg according to the current clock phase. A prototype chip was designed with the 0.18-mum CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement
Keywords :
CMOS integrated circuits; clocks; oscillators; 0.18 micron; 1.25 Gbit/s; 2.5 Gbit/s; CMOS technology; clock phase; doubling data throughput; dual bit-rate burst-mode clock recovery circuits; full-rate clocking mode; gated oscillators; half-rate clocking mode; passive optical network; reset-phase control scheme; CMOS technology; Circuits; Clocks; Delay lines; Frequency; Jitter; Optical receivers; Passive optical networks; Phase locked loops; Voltage-controlled oscillators; Burst-mode clock recovery; dual bit rate; gated oscillator; passive optical network (PON);
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2006.884120
Filename :
4063468
Link To Document :
