Title :
A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-μm GaAs MESFET
Author :
Murata, Koichi ; Otsuji, Taiichi ; Sano, Eiichi ; Ohhata, Masanobu ; Togashi, Minoru ; Suzuki, Masao
Author_Institution :
NTT Opt. Network Syst. Labs., Kanagawa, Japan
fDate :
10/1/1995 12:00:00 AM
Abstract :
This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF´s based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC´s confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s
Keywords :
III-V semiconductors; MESFET integrated circuits; SPICE; circuit analysis computing; decision circuits; delays; field effect logic circuits; flip-flops; gallium arsenide; integrated circuit design; logic design; 0.2 mum; 19 Gbit/s; GaAs; GaAs MESFET; GaAs low-power source-coupled FET logic; SPICE simulation; decision circuit; design methodology; high-speed latching operation flip-flop circuit; high-speed operation mechanism; propagation delay time; series-gated master slave flip-flops; Analytical models; Circuit simulation; Design methodology; FETs; Flip-flops; Gallium arsenide; Logic circuits; Master-slave; Propagation delay; SPICE;
Journal_Title :
Solid-State Circuits, IEEE Journal of
