Title :
Power rail logic: a low power logic style for digital GaAs circuits
Author :
Chandna, Ajay ; Brown, Richard B. ; Putti, David ; Kibler, David C.
Author_Institution :
Joint Motorola/Cascade Libr. Dev. Center., Tempe, AZ, USA
fDate :
10/1/1995 12:00:00 AM
Abstract :
This paper describes a new logic style called Power Rail Logic (PRL), which is compatible with direct-coupled FET logic (DCFL) circuits. Multiplexors, latches, flip-flops, and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-b barrel shifters designed in DCFL and in PRL was successfully fabricated and tested. Test results are given for both circuits
Keywords :
field effect logic circuits; flip-flops; gallium arsenide; logic gates; DCFL compatibility; barrel shifters; digital GaAs circuits; exclusive-OR gates; flip-flops; latches; multiplexors; power rail logic; CMOS logic circuits; Circuit testing; Driver circuits; FETs; Gallium arsenide; Latches; Logic circuits; Logic design; Rails; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
