DocumentCode :
967887
Title :
Hierarchical design methodologies and tools for VLSI chips
Author :
Niessen, C.
Author_Institution :
Philips Research Laboratories, Eindhoven, Netherlands
Volume :
71
Issue :
1
fYear :
1983
Firstpage :
66
Lastpage :
75
Abstract :
Hierarchical design methods are considered to be a means of managing the VLSI design problem. This paper will consider why this problem exists and discuss alternative means that can be used to arrive at a solution. The merits of design methodologies, with emphasis on hierarchical techniques, will be compared with those of automated design approaches. The discussion of hierarchy will lead to the conclusion that the method requires formal abstraction facilities in order to be effective. Hierarchical design methods permit the creation of a new generation of CAD programs that can both give a designer better support and can be much more efficient than the present generation of tools. An example of such a tool, VOILA, will be given.
Keywords :
Design automation; Design methodology; Extrapolation; Impedance; Integrated circuit technology; Integrated circuit yield; Large scale integration; Logic; Productivity; Very large scale integration;
fLanguage :
English
Journal_Title :
Proceedings of the IEEE
Publisher :
ieee
ISSN :
0018-9219
Type :
jour
DOI :
10.1109/PROC.1983.12528
Filename :
1456796
Link To Document :
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