Title :
Minimizing total power by simultaneous Vdd/Vth assignment
Author :
Srivastava, Ashish ; Sylvester, Dennis
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
fDate :
5/1/2004 12:00:00 AM
Abstract :
In this paper, we investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static+dynamic) in generic digital CMOS designs. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1-V processes. Rules-of-thumb are developed for optimal Vdd´s and Vth´s to be used in future designs. These models show the optimal second Vdd to be approximately half the nominal Vdd while the potential total power savings is significantly greater than previously anticipated (60%-65%). We describe the impact of level conversion delays and also demonstrate that the scaling properties of multivoltage systems are very good, particularly when considering impending device scaling advancements.
Keywords :
CMOS digital integrated circuits; circuit CAD; circuit optimisation; circuit simulation; delays; integrated circuit design; integrated circuit modelling; low-power electronics; minimisation; power supply circuits; 60 to 65 percent; IC device scaling; digital CMOS design; dual supply voltage; level conversion delays; multiple supply voltage assignment; multiple threshold voltage assignment; multivoltage systems; power minimization; power reduction; simultaneous Vdd/Vth assignment; Circuit synthesis; Degradation; Delay; Dynamic voltage scaling; Energy consumption; Power supplies; Power system modeling; Process design; Semiconductor device modeling; Threshold voltage;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2004.826551
