A novel circuit technology with surrounding gate transistors (SGT´s) for ultra high density DRAM´s

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT´s) For ultra high density DRAM´s. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGT´s connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V_cc margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL