Monitoring field-programmable gate array-based processing engines of dependable computer systems

The integration of field-programmable gate array (FPGA) devices as co-processing elements in numerous dependable computer systems makes the real-time detection of errors a vital issue. The propagation of FPGA-based application errors can endanger the availability of the hosting computer. Embedded error detection mechanisms should enforce the operation of the FPGA-based systems, in order to prevent system failures. Such monitoring should not interfere with the host PC performance and must also ensure the timely detection of failures. Therefore an embedded error detection and recovery component was designed and implemented, which does not require manual intervention, in order to illustrate the benefits of this approach. A double FPGA board-layout was used to provide the forensic analysis of the dependable workstation´s PCI bus activity. The monitor logic specifically targets PCI buses; it is tightly coupled with the PCI core located in a first FPGA device to check the protocol and application errors in PCI activity. Application circuits are configured in the second FPGA.