DocumentCode
968610
Title
Supply noise and CMOS synchronization errors
Author
Portmann, Clemenz L. ; Meng, Teresa H Y
Author_Institution
Center for Integrated Syst., Stanford Univ., CA, USA
Volume
30
Issue
9
fYear
1995
fDate
9/1/1995 12:00:00 AM
Firstpage
1015
Lastpage
1017
Abstract
The effects of supply disturbances on synchronization failures in CMOS latches are examined. In contrast to prior work, supply noise is shown to increase a synchronizer´s metastability error rate. Buffering the synchronizer to reduce these errors is shown to have little effect on the noise immunity. Measured results are presented from a test setup with a 2-μm CMOS test chip to verify the findings
Keywords
CMOS digital integrated circuits; errors; flip-flops; integrated circuit noise; synchronisation; CMOS latches; CMOS synchronization errors; metastability error rate; noise immunity; supply disturbances; supply noise; synchronization failures; Circuit noise; Circuit simulation; Circuit testing; Clocks; Error analysis; Frequency synchronization; Inverters; Latches; Metastasis; Semiconductor device measurement;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.406400
Filename
406400
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