Low-power chip interconnection by dynamic termination

Author

Kawahara, Takayuki ; Horiguchi, Masashi ; Etoh, Jun ; Sekiguchi, Tomonori ; Kimura, Katsutaka ; Aoki, Masakazu

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

30

Issue

9

fYear

1995

fDate

9/1/1995 12:00:00 AM

Firstpage

1030

Lastpage

1034

Abstract

A low-power dynamic termination scheme is proposed and demonstrated as a way to reduce power dissipation for high-speed data transport. In this scheme, the transmission lines are terminated only if the signals change. The gate of a switching MOS transistor connected to a termination resistor is driven by differentiating the transmission signal with a resistor and a capacitor. The power dissipation of the terminating resistor can be reduced to 1/5 in the conventional determination scheme, and overshoot can be reduced to 1/5 that in the open scheme. This scheme is promising for use with palm-top equipment, facilitating high-speed low power operation

Keywords

BiCMOS digital integrated circuits; CMOS digital integrated circuits; high-frequency transmission lines; integrated circuit interconnections; integrated circuit packaging; dynamic termination; high-speed data transport; high-speed low power operation; low-power chip interconnection; power dissipation; switching MOS transistor; termination resistor; transmission line termination; CMOS technology; Distributed parameter circuits; Frequency; Logic; Optical reflection; Power dissipation; Power transmission lines; Resistors; Termination of employment; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.406404

Filename

406404