• DocumentCode
    968784
  • Title

    Integrated circuit yield statistics

  • Author

    Stapper, Charles H. ; Armstrong, Frederick M. ; Saji, Kiyotaka

  • Author_Institution
    IBM General Technology Division, Essex Junction, VT
  • Volume
    71
  • Issue
    4
  • fYear
    1983
  • fDate
    4/1/1983 12:00:00 AM
  • Firstpage
    453
  • Lastpage
    470
  • Abstract
    The random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process. This approach allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing. Some simpler formulations of yield theory that have been described in the literature are compared to the model. Application of the model to yield management are discussed and examples given.
  • Keywords
    Circuit faults; Circuit testing; Insulation; Integrated circuit packaging; Integrated circuit yield; Manufacturing; Packaging machines; Semiconductor device manufacture; Statistics; Timing;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/PROC.1983.12619
  • Filename
    1456887