DocumentCode :
969562
Title :
Characterizing the Cell EIB On-Chip Network
Author :
Ainsworth, Thomas William ; Pinkston, T.M.
Author_Institution :
Northrop Grumman Space Technol., Redondo Beach
Volume :
27
Issue :
5
fYear :
2007
Firstpage :
6
Lastpage :
14
Abstract :
On-chip network design has become an increasingly important component of computer architecture. the cell broadband engine´s element interconnect bus, with its four data rings and common command bus for end-to-end transaction control, interconnects more nodes than most commercial on- chip networks. to help understand on-chip network design and performance issues in the context of a commercial multicore chip, this article evaluates the ElB network using conventional latency and throughput characterization methods.
Keywords :
computer architecture; network-on-chip; system buses; commercial on-chip network; computer architecture; element interconnect bus; end-to-end transaction control; on-chip network design; Bandwidth; Computer networks; Costs; Delay; Engines; Multicore processing; Network-on-a-chip; Power system reliability; Random access memory; Throughput; interconnection architectures; multicore architectures; multiple data stream architectures; multiprocessors; on-chip interconnection networks;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/MM.2007.4378779
Filename :
4378779
Link To Document :
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