On-Chip Interconnection Architecture of the Tile Processor

Author

Wentzlaff, D. ; Griffin, P. ; Hoffmann, H. ; Liewei Bao ; Edwards, Ben ; Ramey, C. ; Mattina, M. ; Chyi-Chang Miao ; Brown, J.F. ; Agarwal, A.

Author_Institution

Massachusetts Inst. of Technol, Cambridge

Volume

27

Issue

5

fYear

2007

Firstpage

15

Lastpage

31

Abstract

IMesh, the tile processor architecture´s on-chip interconnection network, connects the multicore processor´s tiles with five 2D mesh networks, each specialized for a different use. taking advantage of the five networks, the C-based ILIB interconnection library efficiently maps program communication across the on-chip interconnect. the tile processor´s first implementation, the tile64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 Ghz.

Keywords

computer architecture; multiprocessor interconnection networks; network-on-chip; 2D mesh network; C-based ILIB interconnection library; onchip interconnection architecture; tile processor; Bandwidth; Communication networks; Computer architecture; Hardware; Mesh networks; Multicore processing; Multiprocessor interconnection networks; Network-on-a-chip; MIMD processors; mesh networks; multicore architectures; on-chip interconnection networks; parallel architectures;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2007.4378780

Filename

4378780