Abstract :
Programming MPPAs for complex real-time embedded applications is difficult with conventional multiprogramming models, which usually treat communication and synchronization separately. Based on a programming model for massively parallel embedded computing that is reasonable and productive for software developers, we developed a scalable MPPA chip architecture that delivers tera-ops performance with very good energy efficiency in an ordinary 130-nm ASIC. This MPPA´s architecture is based on the structural object programming model, which composes strictly encapsulated processing and memory objects in a structure of self-synchronizing channels. Small RISC CPUs and memories execute the objects.
Keywords :
embedded systems; microprocessor chips; multiprogramming; object-oriented programming; parallel architectures; reduced instruction set computing; synchronisation; system-on-chip; MPPA chip architecture; MPPA programming; RISC CPU; massively parallel embedded computing; massively parallel processor array; real-time embedded applications; self-synchronizing channels; structural object programming model; Application software; Application specific integrated circuits; Computer architecture; High definition video; Integrated circuit interconnections; Packet switching; Parallel programming; Reduced instruction set computing; Registers; Sensor arrays; multicore architectures; multiple data stream processors; multiprocessors; parallel architectures; synchronization;
