A digitally controlled PLL for SoC applications

Author

Olsson, Thomas ; Nilsson, Peter

Author_Institution

Lund Univ., Sweden

Volume

39

Issue

5

fYear

2004

fDate

5/1/2004 12:00:00 AM

Firstpage

751

Lastpage

760

Abstract

A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-μm standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm². In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.

Keywords

CMOS digital integrated circuits; clocks; digital phase locked loops; hardware description languages; multiplying circuits; system-on-chip; 0.35 microns; 152 to 366 MHz; 3 V; IP block; SoC applications; all-digital PLL; clock multiplying circuit; digital standard cell libraries; digital system simulation; digitally controlled PLL; digitally controlled oscillator; digitally controlled phase-locked loop; fully integrated phase-locked loop; off-chip components; standard CMOS process; synthesizable VHDL code; time-to-digital converter; CMOS process; CMOS technology; Clocks; Digital control; Frequency; Integrated circuit technology; Multiplying circuits; Phase locked loops; Software libraries; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.826333

Filename

1291680