Bringing NoCs to 65 nm

Author

Pullini, Antonio ; Angiolini, Federico ; Murali, Srinivasan ; Atienza, David ; De Micheli, Giovanni ; Benini, Luca

Author_Institution

Politecnico di Torino, Turin

Volume

27

Issue

5

fYear

2007

Firstpage

75

Lastpage

85

Abstract

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The experimental results from fully working 65-nm NoC designs and a detailed scalability analysis are presented. The network on chip (NoC) is a promising solution to the scalability problem. NoCs build upon improvements in bus architecture-for example, in terms of topology design.

Keywords

CMOS integrated circuits; integrated circuit design; integrated circuit interconnections; network-on-chip; NoC-based interconnect design; bus architecture; nanometer CMOS; network-on-chip; scalability analysis; very deep submicron process technology; Bandwidth; Bridges; Crosstalk; Network topology; Network-on-a-chip; Propagation delay; Protocols; Scalability; Switches; Wires; deep submicron design; design aids; low-power design; multicore architectures; network on chip; on-chip interconnection networks; power management;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2007.4378785

Filename

4378785