Title :
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link
Author :
Moon, Yongsam ; Park, Young-Soo ; Kim, Namhoon ; Ahn, Gijung ; Shin, Hyun J. ; Jeong, Deog-Kyoon
Author_Institution :
Silicon Image Inc., Sunnyvale, CA, USA
fDate :
5/1/2004 12:00:00 AM
Abstract :
A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled-oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-μm CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10-13.
Keywords :
CMOS integrated circuits; delay lock loops; interference (signal); jitter; phase locked loops; transceivers; voltage-controlled oscillators; 0.18 microns; 0.6 to 3.2 Gbit/s; AT-fold voltage-controlled- oscillator; CMOS technology; VCO gain reduction; analog coarse-tuning scheme; backplane serial link; clock generator; clock recovery circuit; data recovery circuit; delayed-locked loop; elastic buffer; fixed-interval charge pumping; folded starved inverter; interchannel interference; interference-free CMOS transceiver; noise immunity; phase-locked loops; quad-channel CMOS transceiver; random jitter performance; reset generator; seamless frequency acquisition; Backplanes; CMOS technology; Frequency; Interchannel interference; Inverters; Jitter; Noise reduction; Phase locked loops; Transceivers; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.826311
