A low-power ASIC design for cell search in the W-CDMA system

Author

Li, Chi-Fang ; Chu, Yuan-Sun ; Sheen, Wern-Ho ; Tian, Fu-Chin ; Ho, Jan-Shin

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Cheng Univ., Chia-Yi, Taiwan

Volume

39

Issue

5

fYear

2004

fDate

5/1/2004 12:00:00 AM

Firstpage

852

Lastpage

857

Abstract

This paper presents a low-power ASIC design for cell search in the wideband code-division multiple-access (W-CDMA) system. A low-complexity algorithm that is able to work satisfactorily under the effect of large frequency and clock errors is designed first. Then, a set of low-power measures are employed in the design of hardware architecture and circuits. Finally, through power analysis, critical blocks are identified and redesigned so as to further reduce the power consumption. The final design shows that the power is reduced by 51% from the original design of 133.6 mW to 65.49 mW, and its core area is also reduced by 31.9% from 3.4×3.4 mm² to 2.8×2.8 mm². The design is implemented and verified in a 3.3-V 0.35-μm CMOS technology with clock rate 15.36 MHz.

Keywords

CMOS integrated circuits; application specific integrated circuits; broadband networks; cellular radio; code division multiple access; integrated circuit design; low-power electronics; 0.35 microns; 133.6 mW; 15.36 MHz; 3.3 V; 65.49 mW; CMOS technology; W-CDMA system; cell search; clock errors; frequency error; low-complexity algorithm; low-power ASIC design; low-power design; power analysis; power consumption reduction; Algorithm design and analysis; Application specific integrated circuits; Base stations; CMOS technology; Clocks; Energy consumption; Frequency synchronization; Hardware; Multiaccess communication; Wideband;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.826337

Filename

1291692