A low-power ASIC design for cell search in the W-CDMA system

This paper presents a low-power ASIC design for cell search in the wideband code-division multiple-access (W-CDMA) system. A low-complexity algorithm that is able to work satisfactorily under the effect of large frequency and clock errors is designed first. Then, a set of low-power measures are employed in the design of hardware architecture and circuits. Finally, through power analysis, critical blocks are identified and redesigned so as to further reduce the power consumption. The final design shows that the power is reduced by 51% from the original design of 133.6 mW to 65.49 mW, and its core area is also reduced by 31.9% from 3.4×3.4 mm² to 2.8×2.8 mm². The design is implemented and verified in a 3.3-V 0.35-μm CMOS technology with clock rate 15.36 MHz.