DocumentCode :
969808
Title :
Die Attach Evaluation Using Test Chips Containing Localized Temperature Measurement Diodes
Author :
Anderman, Jeffrey ; Tustaniwskyj, Jerry ; Usell, Ray
Author_Institution :
University of California, Los Angeles, CA
Volume :
9
Issue :
4
fYear :
1986
fDate :
12/1/1986 12:00:00 AM
Firstpage :
410
Lastpage :
415
Abstract :
The die attach related problems of lifting and die cracking become more critical with increasing size of integrated circuit (IC) devices. For this reason, a thermal test utilizing specialized chips and an automated system has been designed for the evaluation of large die attach integrity. Both void detection and statistical characterization of sample populations are possible. While an actual estimation of void size is not made, a quantitative evaluation by comparison is established. The correlation of test measurements with die attach related failures provides a useful tool for process evaluation. Examples of studies done with gold-silicon eutectic die attach are discussed.
Keywords :
Integrated circuit bonding; Integrated circuit reliability; Integrated circuit thermal factors; Assembly; Circuit testing; Diodes; Microassembly; Packaging; Silicon; Surface cracks; Temperature measurement; Tensile stress; Thermal stresses;
fLanguage :
English
Journal_Title :
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
0148-6411
Type :
jour
DOI :
10.1109/TCHMT.1986.1136681
Filename :
1136681
Link To Document :
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