DocumentCode :
970098
Title :
Use of Low-Density Parity-Check Codes for Dominant Error Events Detection and k -Constraint Enforcement
Author :
Sun, Fei ; Zhang, Tong
Author_Institution :
Marvell Semicond., Santa Clara
Volume :
43
Issue :
12
fYear :
2007
Firstpage :
4113
Lastpage :
4116
Abstract :
In this paper, we propose to leverage the simple and explicit parity checks inherent in low-density parity-check (LDPC) codes to detect dominant error events without code rate penalty. This is enabled by enforcing a very weak constraint on the LDPC code parity check matrix structure. Such a constraint can be readily satisfied by most structured LDPC codes reported in the open literature, such as quasi-cyclic (QC) LDPC codes. Moreover, this zero-redundancy dominant error events detection can be extended to handle the bit errors that occur when deliberate bit-flipping is used to enforce -constraints. We have demonstrated the effectiveness of the proposed method in computer simulations.
Keywords :
error correction codes; error statistics; magnetic recording; dominant error events detection; k-constraint enforcement; low-density parity-check codes; quasi-cyclic LDPC codes; zero-redundancy dominant error; $k$-constraint; Dominant error events; low-density parity-check (LDPC);
fLanguage :
English
Journal_Title :
Magnetics, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9464
Type :
jour
DOI :
10.1109/TMAG.2007.907329
Filename :
4380282
Link To Document :
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