DocumentCode
970260
Title
A Novel Planar Multilevel Interconnection Technology Utilizing Polyimide
Author
Sato, Kikuji ; Harada, Seiki ; Saiki, Atsushi ; Kimura, Takeshi ; Okubo, Toshio ; Mukai, Kiichiro
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
9
Issue
3
fYear
1973
fDate
9/1/1973 12:00:00 AM
Firstpage
176
Lastpage
180
Abstract
A completely new planar method permitting step-free multilevel interconnections is proposed. The key role in this technique is played by the polyimide film which is used as insulating layers. The fluid property of the polymer solution always gives an ideal flatness to the surface of the wafer no matter how many steps are formed by preceding metallization processes. Using this planar metallization with polymer (PNIP) technique, a five-level structure which consists of five metal (aluminum) and five polyimide layers has been successfully made, The PMP structure completely eliminates the failures which result from open circuits between metal layers at crossovers and via-holes and from short circuits between metal layers through the pin-holes of insulating layers. No trace of degradation is observed in the characteristics of the MOS-FET covered with the polyimide either after heating at 150°c for 2000 hours or after a bias-temperature test at 125°c for 200 hours.
Keywords
Integrated circuit interconnections; Interconnections, Integrated circuits; LSI; Polyimide films; Aluminum; Circuit testing; Degradation; Heating; Integrated circuit interconnections; Metallization; Plastic insulation; Polyimides; Polymers; Portable media players;
fLanguage
English
Journal_Title
Parts, Hybrids, and Packaging, IEEE Transactions on
Publisher
ieee
ISSN
0361-1000
Type
jour
DOI
10.1109/TPHP.1973.1136727
Filename
1136727
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