• DocumentCode
    970400
  • Title

    An efficient multilayer MCM router based on four-via routing

  • Author

    Khoo, Kei-Yong ; Cong, Jason

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
  • Volume
    14
  • Issue
    10
  • fYear
    1995
  • fDate
    10/1/1995 12:00:00 AM
  • Firstpage
    1277
  • Lastpage
    1290
  • Abstract
    In this paper, we present an efficient multilayer general area router, named V4R, for MCM and dense PCB designs. One unique feature of the V4R router is that it uses no more than four interconnection vias to route every net and yet produces high quality routing solutions. Another unique feature of the V4R router is it combines global routing and detailed routing in one step and produces high quality detailed routing solutions directly from the given netlist and module placement. Several combinatorial optimization techniques, including efficient algorithms for computing a maximum weighted k-cofamily in a partially ordered set and a maximum weighted noncrossing matching in a bipartite graph, are used to solve the combined problem efficiently. As a result, the V4R router is independent of net ordering, runs much faster, and uses far less memory compared to other multilayer general area routers. We tested our router on several examples, including three industrial MCM designs from MCC. Compared with the 3-D maze router, on average the V4R router uses 44% fewer vias, 2% less wirelength, and runs 26 times faster. Compared with the SLICE router, on average the V4R router uses 9% fewer vias, 4% less wirelength, and runs 3.5 times faster. The V4R also uses fewer routing layers compared to the 3-D maze router and the SLICE router
  • Keywords
    circuit layout CAD; circuit optimisation; graph theory; multichip modules; network routing; printed circuit layout; V4R router; bipartite graph; circuit layout; combinatorial optimization techniques; dense PCB design; detailed routing; four-via routing; global routing; multilayer MCM router; multilayer general area router; partially ordered set; Bipartite graph; Ceramics; Design methodology; Integrated circuit interconnections; Multichip modules; Nonhomogeneous media; Packaging; Routing; Supercomputers; Testing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.466343
  • Filename
    466343