Processes for Fabricating a Planar P-N-P Silicon Transistor

Processes and techniques required for fabrication of experimental planar p-n-p silicon transistors have been developed and demonstrated as feasible. Processes involved include material preparation, antimony base diffusion, boron emitter diffusion, oxide masking, photoresist techniques, simultaneous gold metalizing of emitter and base regions, collector alloy contact and basing and thermocompression bonding. Initial transistors have typical dc Beta values of 35 to 40 and FTvalues as high as 250 Mc. Processes described have also been used in preliminary fabrication of solid-state microcircuit passive components.