DocumentCode :
970925
Title :
An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization
Author :
Jung Sub Kim ; Lanping Deng ; Mangalagiri, P. ; Irick, K. ; Sobti, K. ; Kandemir, M. ; Narayanan, V. ; Chakrabarti, C. ; Pitsianis, N. ; Xiaobai Sun
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Volume :
58
Issue :
12
fYear :
2009
Firstpage :
1654
Lastpage :
1667
Abstract :
This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Applications utilizing numerical algorithms on large-size data sets require high-throughput computation platforms. The focus is on N-body interaction problems which have a wide range of applications spanning from astrophysics to molecular dynamics. The TANOR design flow starts with a MATLAB description of a particular interaction function, its parameters, and certain architectural constraints specified through a graphical user interface. Subsequently, TANOR automatically generates a configuration bitstream for a target FPGA along with associated drivers and control software necessary to direct the application from a host PC. Architectural exploration is facilitated through support for fully custom fixed-point and floating-point representations in addition to standard number representations such as single-precision floating point. Moreover, TANOR enables joint exploration of algorithmic and architectural variations in realizing efficient hardware accelerators. TANOR´s capabilities have been demonstrated for three different N-body interaction applications: the calculation of gravitational potential in astrophysics, the diffusion or convolution with Gaussian kernel common in image processing applications, and the force calculation with vector-valued kernel function in molecular dynamics simulation. Experimental results show that TANOR-generated hardware accelerators achieve lower resource utilization without compromising numerical accuracy, in comparison to other existing custom accelerators.
Keywords :
application specific integrated circuits; field programmable gate arrays; logic design; mathematics computing; reconfigurable architectures; ASIC; FPGA; MATLAB description; N-body interaction problems; TANOR design flow; algorithmic-architectural optimization; control software; custom fixed-point; drivers; field- programmable gate arrays; floating-point representations; graphical user interface; hardware accelerators; high-throughput computation platforms; host PC; image processing applications; molecular dynamics simulation; numerical algorithms; reconfigurable platforms; single-precision floating point; vector-valued kernel function; with Gaussian kernel; Accuracy; Algorithm design and analysis; Field programmable gate arrays; Hardware; MATLAB; Numerical analysis; Algorithms implemented in hardware; numerical algorithms.; reconfigurable hardware; signal processing systems;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2009.78
Filename :
5010433
Link To Document :
بازگشت