Title :
High-performance devices for a 0.15- mu m CMOS technology
Author :
Shahidi, G.G. ; Warnock, James ; Fischer, S. ; McFarland, P.A. ; Acovic, Alexandre ; Subbanna, S. ; Ganin, E. ; Crabbé, Emmanuel ; Comfort, James ; Sun, Jack Y C ; Ning, Tak H. ; Davari, Bijan
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF/sub 2/ implant were used. Maximum high V/sub DS/ threshold rolloff was 250 mV at effective channel length of 0.06 mu m. For the minimum channel length of 0.1 mu m, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively.<>
Keywords :
CMOS integrated circuits; doping profiles; integrated circuit technology; semiconductor doping; 0.06 to 0.15 micron; 0.1 micron; BF/sub 2/ implant; CMOS technology; In preamorphisation; Sb preamorphization; Si:B,Sb; Si:In; Si:In,As; Si:Sb; channel lengths; low energy As implant; nonuniform channel dopings; short-channel effects; submicron IC technology; CMOS process; CMOS technology; Capacitance; Delay; Doping; Implants; Indium; Lifting equipment; MOS devices; Sun;
Journal_Title :
Electron Device Letters, IEEE
