DocumentCode
972049
Title
An evaluation of FUROX isolation technology for VLSI/nMOSFET fabrication
Author
Tsai, Hong-Hsiang ; Chen, Shiao-Mo ; Chen, Huang-Ben ; Wu, Ching-Yuan
Author_Institution
Coll. of Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Volume
35
Issue
3
fYear
1988
fDate
3/1/1988 12:00:00 AM
Firstpage
275
Lastpage
284
Abstract
A defect-free near-zero bird´s beak, fully recessed oxide (FUROX) field-isolation technology has been evaluated through the fabrication of VLSI/nMOSFETs. The FUROX process mainly consists of: (1) a thin nitrided oxide as the stress buffer layer and the interface sealing layer for local oxidation enhancement; and (2) a novel more-reliable nitride masking structure for a two-step field oxidation and a self-aligned field implantation. The elimination of the necking effect on positive photoresist and the improvement of critical dimension control for polysilicon gates using the planarized isolation have been demonstrated. Through electrical characterization of n+-p diodes and field and active transistors, the FUROX devices have been shown to provide low leakage-current level, good isolation property, and large recovery of the effective channel width (1.4 μm). Therefore, the serious narrow-width effects that exist in conventional LOCOS (local oxidation of silicon) isolated have been effectively reduced. Using histogram analysis, the reliability of the masking structure had hence good uniformity of device properties for FUROX isolation have been exhibited. The successful fabrication of FUROX devices with W eff=0.6 μm clearly demonstrates that FUROX isolation technology is greatly superior to conventional LOCOS
Keywords
VLSI; field effect integrated circuits; insulated gate field effect transistors; integrated circuit technology; oxidation; 1.4 micron; FUROX isolation technology; Si-SiNxOy-Si3N4-SiO 2; VLSI; defect-free near-zero bird´s beak; effective channel width; histogram analysis; interface sealing layer; local oxidation enhancement; low leakage-current level; n-MOSFET; n+-p diodes; nitride masking structure; polysilicon gates; reliability; self-aligned field implantation; stress buffer layer; thin nitrided oxide; two-step field oxidation; Buffer layers; Diodes; Fabrication; Isolation technology; MOSFET circuits; Oxidation; Resists; Silicon; Stress; Very large scale integration;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.2451
Filename
2451
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