Title :
Analysis for optimum threshold voltage and load current of E-D-type GaAs DCFL circuits
Author :
Ino, M. ; Hirayama, Motoko ; Ohmori, Masato
Author_Institution :
NTT, Musashino Electrical Communication Laboratory, Musashino, Japan
Abstract :
A GaAs MESFET E-D invertor was analysed to estimate the optimum threshold voltage VT for a switching FET, and the optimum load current IL for a load FET, that will minimise the invertor switching time. The calculated results show that the optimum VT lies at around 0.2 V, and the optimum IL is about 55% of the saturation current of the switching FET.
Keywords :
III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated logic circuits; invertors; E-D-type GaAs DCFL circuits; GaAs MESFET E-D invertor; invertor switching time; load FET; logic circuit; optimum load current; optimum threshold voltage; switching FET;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19810365
