Title :
An Error-Correcting Encoder and Decoder of High Efficiency
Author :
Green, J.H., Jr. ; Soucie, R. L San
Author_Institution :
Sylvania Electronics Sys., Amherst Eng. Labs., Williamsville, N.Y.
Abstract :
A report is given on a group effort which has demonstrated the applicability of regenerative shift register sequences to error-correcting codes. It is shown that a triple-error-correcting code of high efficiency can be formed by using the 15 cyclic permutations of a 15-bit, maximal-length, shift register sequence, a 15-bit zero sequence, and the 1-0 complements of the 16 sequences. It is further shown that the interrelationships between the bits of these binary sequences can be used to design a decoder of extreme simplicity.
Keywords :
Adders; Binary sequences; Code standards; Communication systems; Encoding; Error correction codes; Iterative decoding; Laboratories; Shift registers; Storage area networks;
Journal_Title :
Proceedings of the IRE
DOI :
10.1109/JRPROC.1958.286754
