Title :
An accurate gate length extraction method for sub-quarter micron MOSFET´s
Author :
Huang, Cheng-Liang ; Faricelli, John V. ; Antoniadis, Dimitri A. ; Khalil, Nadim A. ; Rios, Rafael A.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
fDate :
6/1/1996 12:00:00 AM
Abstract :
By comparing measured and simulated gate-to-source/drain capacitances, Cgds, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET´s applications. We show that by including the 2-D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the Cgds simulation, the polysilicon gate length, Lpoly, can be accurately determined for device lengths down to the 0.1 μm regime. The accuracy of this method approaches that of cross-sectional TEM on the device under test, but without destroying the device. Furthermore, we note that as a result of accurate Lpoly extraction, the source/drain lateral diffusion length, Ldiff , and effective channel length, Leff, can also be determined precisely. The accuracy of Ldiff is confirmed by examining their consistency with experimentally obtained 2-D source/drain profile
Keywords :
MOSFET; capacitance; semiconductor device models; silicon; 0.25 micron; 2D field effect; Si; effective channel length; fringing capacitance; gate length extraction method; gate-to-source/drain capacitances; polysilicon depletion; quantum-well effects; simulation; source/drain lateral diffusion length; sub-quarter micron MOSFET; CMOS process; CMOS technology; Capacitance measurement; Capacitance-voltage characteristics; Length measurement; MOSFET circuits; Monitoring; Quantum well devices; Scanning electron microscopy; Testing;
Journal_Title :
Electron Devices, IEEE Transactions on
